(1) Field of the Invention
The present invention relates to the field of fabricating semiconductor devices, and more particularly, to making electrical contacts to semiconductor device regions and interlayer interconnects.
(2) Prior Art
In the fabrication of integrated circuits, it is often desired to etch certain areas of a dielectric or insulating film (i.e., SiO.sub.2) formed over a semiconductor substrate (i.e., Si) to create via or contact holes for electrically contacting certain regions of the device, such as the source and drain regions of a transistor. However, as the size of semiconductor device features are significantly reduced to meet the needs of today's very large scale integration (VLSI) technology, the problem of making reliable electrical contacts to the regions of the device through established via and contact holes is worsened.
Because the significant reduction in the size of the device features requires that the holes be positioned close together, be of small diameter and have steep vertical sidewalls, it has become difficult to deposit conventional materials (i.e., aluminum) in the holes such that a uniform contact with the underlying conductive region or layer is established and no breaks occur in the interconnect metalization at the edges of the holes. As shown in FIG. 1(a), this is partially overcome in the prior art by filling, for example, the contact holes (either selectively or not) with a separate plug fill material such as tungsten and then depositing an aluminum metalization over the plug to form an interconnect or landing pad (see for example U.S. Pat. Nos. 4,822,753 and 4,960,732). In this manner, the aluminum interconnect or landing pad does not traverse the acute edge of the contact hole where electrical breaks are likely to occur during formation of the interconnect.
According to more recent methods designed to eliminate the problem of tungsten not adhering to silicon dioxide, a tungsten plug fill material is deposited as a blanket layer over an underlying conductive film (e.g., titanium, titanium-nitride, titanium-tungsten, etc.) which serves as an adhesion layer for the adhesion of tungsten to the silicon dioxide insulating layer (see FIG. 1(b)). Following etch-back of the tungsten blanket layer, an additional conductive layer (e.g., titanium, titanium-nitride, titanium-tungsten, aluminum, etc.) is applied over the plug and is subsequently patterned and etched leaving an interconnect between via plugs and/or a landing pad layer for a subsequent overlying via. Using this conventional method, however, forces the conduction path of the interconnect or landing pad to cross two interfaces through the via, namely (i) the interface between the interconnect and the plug; and (ii) the interface between the plug and the adhesion layer. These interfaces, which are depicted as Interfaces #1 and #2 in FIG. 1(b), will result in an increased resistance of the electrical contacts, thereby reducing the speed of the semiconductor device.
Another disadvantage with the above method is that enclosure or coverage of the contact or via hole by the interconnect or landing pad is dependent upon their alignment to the hole during patterning using a masking layer such as a photoresist. If the masking layer is not properly aligned with the hole, partial enclosure, or perhaps even complete non-enclosure of the hole will result, again causing the resistance of the contact to substantially increase or a complete failure of the electrical contact.
Another method designed to overcome the above-noted problems is the use of tungsten for both the plug fill material and the interconnect wiring layer, with the plug and wiring layer being formed through chemical vapor deposition (CVD) or bias sputtering and an etch back step (see for example U.S. Pat. Nos. 4,960,732 and 5,183,782). Since modern tungsten deposition techniques overcome the problem of electrical breaks forming at the edges of the hole, the blanket layer of tungsten overlying the insulating (or other adhesive and/or barrier) layers can simply be patterned and etched to form the electrical wiring associated with the plug of the hole. This combined plug and interconnect structure eliminates the interfaces described above in addition to alleviating the alignment-dependency problem. Yet, the use of tungsten itself as the interconnect layer introduces an additional planarity problem due to the formation of an interconnect having rather large step features at its edges. This arises from the fact that a significant amount of Tungsten must be deposited over the entire surface of the semiconductor to ensure that the hole is completely filled, but this also results in a significant increase in the thickness of the interconnect portion itself.
Yet another prior art method, which is designed to avoid the problems of encroachment at the silicon-to-silicon dioxide interface, worm hole damage to the underlying silicon and the line electromigration susceptibility of aluminum interconnects, is described in U.S. Pat. No. 4,960,732. According to that reference, an adhesion layer comprising Titanium is first deposited within a contact hole followed by a barrier layer of a refractory metal that acts as a barrier to silicon diffusion. After an annealing step, Tungsten is then deposited or sputtered on the surface of the device and removed from everywhere expect within the contact hole by use of an etch back step. The etch back step is selective with respect to the barrier layer such that both the adhesion and barrier layers remain on the silicon dioxide surface. A subsequent overlying aluminum metalization step in addition to both a patterning step and etch back step are then used to form an interconnect comprising the aluminum layer and both the adhesion and barrier layers for electrically contacting the tungsten plug within the contact hole.
Although the formation of the above-described interconnect structure resolves many of the prior art problems, it still does not satisfactorily resolve the electrical interface barrier and planarity problems set forth above. Because this interconnect actually forms a three level structure comprising the adhesion layer, the barrier layer and the aluminum layer, two electrical interface barriers still exist as shown in FIG. 1(c), thereby resulting in slower device speeds. Additionally, aside from the fact that this three tiered structure also increases the required number of process steps, it further increases the total thickness of the interconnect, which is approximately 2300 angstroms. With an interconnect of such thickness, the poor step coverage that results from the formation of additional overlying layers causes a loss of planarity in the semiconductor. This may then require the inclusion of further planarization steps (i.e., polishing) in order to reduce its thickness to within a range acceptable for use of high numerical aperture lithography.